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July 1997 PRELIMINARY
ML6697 100BASE-TX Physical Layer with MII
GENERAL DESCRIPTION
The ML6697 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6697 offers a single-chip per-port solution for MII-based repeater applications. The ML6697 interfaces to the controller through the Media Independent Interface (MII). The ML6697 functionality includes 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz clock recovery/generation, receive adaptive equalization, baseline wander correction, and MLT-3 transmitter.
FEATURES
n Single-chip 100BASE-TX physical layer n Compliant to IEEE 802.3u 100BASE-TX standard n Supports MII-based repeater applications n Compliant MII (Media Indendent Interface) n 4B/5B encoder/decoder n Stream Cipher scrambler/descrambler n 125MHz clock recovery/generation n Baseline wander correction n Adaptive equalization and MLT-3 encoding/decoding
BLOCK DIAGRAM (PLCC Package)
1 9
TXCLKIN TXCLK
CLOCK SYNTHESIZER
3 4 5 6 7 8
TXD3 TXD2 TXD1 TXD0 TXEN TXER CRS RXEN RXCLK RXD3 RXD2 RXD1 RXD0 RXDV RXER
PCS TRANSMIT STATE MACHINE 4B/5B ENCODER SCRAMBLER NRZ TO NRZI ENCODER SERIALIZER MLT-3 ENCODER FLP/100BASE-TX TWISTED PAIR DRIVER
TPOUTP TPOUTN RTSET
40 39 37
18 19 17 10 12 14 16 21 23
CLOCK AND DATA RECOVERY NRZI TO NRZ DECODER PCS RECEIVE STATE MACHINE 5B/4B DECODER DESCRAMBLER MII MANAGEMENT REGISTERS AND CONTROL LOGIC DESERIALIZER
EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX
TPINP TPINN CMREF RGMSET LINK100
45 44 46 36 43
PHYAD0
PHYAD1
PHYAD2
PHYAD3
32
24
25
29
30
31
PHYAD4
33
MDIO
MDC
1
ML6697
PIN CONFIGURATION
ML6697 52-Pin PLCC (Q52)
TXCLKIN
AGND1
AVCC1
TXD0
TXD1
TXD2
TXD3
TXEN
NC
NC
NC
NC
7 TXER TXCLK RXD3 DGND1 RXD2 DVCC1 RXD1 DGND2 RXD0 RXCLK CRS RXEN DGND3 8 9 10 11 12 13 14 15 16 17 18 19 20 21
RXDV
6
5
4
3
2
1
52
51
50
49
48
47 46 45 44 43 42 41 40 39 38 37 36 35 34 CMREF TPINP TPINN LINK100 AVCC2 AGND2 TPOUTP TPOUTN AGND3 RTSET RGMSET AVCC3B AVCC3A
22 23
DVCC2 RXER
24
MDC
25
MDIO
26
DGND4
27
DVCC5
28
DGND5
29
PHYAD0
30
PHYAD1
31
PHYAD2
32
PHYAD3
33
PHYAD4
2
NC
ML6697
PIN CONFIGURATION (Continued)
ML6697 64-Pin TQFP (H64-10)
AGND1A
AGND1B
TXCLKIN
AVCC1
TXD0
TXD1
TXD2
TXD3
TXEN
TXER
NC
NC
NC
NC
NC
50
64 TXCLK RXD3 DGND1A DGND1B RXD2 DVCC1A DVCC1B RXD1 DGND2A DGND2B RXD0 RXCLK CRS RXEN DGND3A DGND3B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
63
62
61
60
59
58
57
56
55
54
53
52
51
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC CMREF TPINP TPINN LINK100 AVCC2 AGND2A AGND2B TPOUTP TPOUTN AGND3A AGND3B RTSET RGMSET AVCC3B AVCC3A
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RXDV
DVCC2
RXER
MDC
DGND4B
DVCC5A
DVCC5B
DGND5B
PHYAD0
PHYAD1
PHYAD2
PHYAD3
DGND4A
DGND5A
PHYAD4
MDIO
NC
3
ML6697
PIN DESCRIPTION (Pin numbers for TQFP package in parentheses)
PIN NAME DESCRIPTION
1
(56)
TXCLKIN
Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal transmit PLL clock multiplier. This pin should be driven by an external 25MHz clock at TTL or CMOS levels. Analog ground. Transmit data TTL inputs. TXD<3:0> inputs accept TX data from the MII. Data appearing at TXD<3:0> are clocked into the ML6697 on the rising edge of TXCLK. Transmit enable TTL input. Driving this input high indicates to the ML6697 that transmit data are present at TXD<3:0>. TXEN edges should be synchronous with TXCLK. Transmit error TTL input. Driving this pin high with TXEN also high causes the part to continuously transmit scrambled H symbols. When TXEN is low, TXER has no effect. Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6697 on the rising edge of this clock. Receive data TTL outputs. RXD<3:0> outputs are valid on RXCLK's rising edge. Digital ground. Digital +5V power supply. Digital ground. Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at TPINP/N. Receive data at RXD<3:0> changes on the falling edges and should be sampled on the rising edges of this clock. RXCLK is phase aligned to TXCLKIN when the 100BASE-TX signal is not present at TPINP/N. Carrier Sense TTL output. CRS goes high in the presence of non-idle signals at TPINP/ N. CRS goes low when receive is idle. Receive enable TTL input. When this input is high, all the MII TTL outputs are enabled. When this input is low, all the MII TTL outputs are in high impedance mode. This input does not affect MDIO, TXCLK and CRS. Digital ground. Receive data valid TTL output. This output goes high when the ML6697 is receiving a data packet. RXDV should be sampled synchronously with RXCLK's rising edge. Digital +5V power supply. Receive error TTL output. This output goes high to indicate error or invalid symbols within a packet, or corrupted idle between packets. RXER should be sampled synchronously with RXCLK's rising edge. MII Management Interface clock TTL input. A clock at this pin clocks serial data into or out of the ML6697's MII management registers through the MDIO pin. The maximum clock frequency at MDC is 2.5MHz.
2 3, 4 5, 6 7
(58, 57) (59,60, 61,62) (63)
AGND1 TXD<3:0> TXEN
8
(64)
TXER
9
(1)
TXCLK
10, 12, (2, 5, 14, 16 8, 11) 11 13 15 17 (3, 4) (6, 7) (9, 10) (12)
RXD<3:0> DGND1 DVCC1 DGND2 RXCLK
18 19
(13) (14)
CRS RXEN
20 21 22 23
(15, 16) (17) (18) (19)
DGND3 RXDV DVCC2 RXER
24
(20)
MDC
4
ML6697
PIN DESCRIPTION (Continued)
PIN NAME DESCRIPTION
25
(21)
MDIO
MII Management Interface data TTL input/output. Serial data are written to and read from the ML6697's management registers through this I/O pin. Input data is sampled on the rising edge of MDC. Data output should be sampled synchronously with MDC's rising edge. Digital ground. Digital +5V power supply. Digital ground. MII Serial Management Interface address bit 0. MII Serial Management Interface address bit 1. MII Serial Management Interface address bit 2. MII Serial Management Interface address bit 3. MII Serial Management Interface address bit 4. Analog +5V power supply. Analog +5V power supply. Equalizer bias resistor input. An external 9.53kW, 1% resistor connected between RGMSET and AGND3 sets internal time constants controlling the receive equalizer transfer function. Transmit level bias resistor input. An external 2.49kW, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit level. Analog ground. Transmit twisted pair outputs. This differential current output pair drives MLT-3 waveforms into the network coupling transformer. Analog ground. Analog +5V power supply. 100BASE-TX link activity open-drain output. LINK100 pulls low when there is 100BASE-TX activity at TPINP/N in 100BASE-TX or auto-negotiation modes. This output is capable of driving an LED directly. Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals from the network. Receiver common-mode reference output. This pin provides a common-mode bias point for the twisted-pair media line receiver, typically (VCC - 1.26)V. Analog +5V power supply.
26 27 28 29 30 31 32 33 34 35 36
(22, 23) (24, 25) (26, 27) (28) (29) (30) (31) (32) (33) (34) (35)
DGND4 DVCC5 DGND5 PHYAD0 PHYAD1 PHYAD2 PHYAD3 PHYAD4 AVCC3A AVCC3B RGMSET
37
(36)
RTSET
38
(37, 38)
AGND3 TPOUTN/P AGND2 AVCC2 LINK100
39, 40 (39, 40) 41 42 43 (41, 42) (43) (44)
44, 45 (45, 46) 46 52 (47) (55)
TPINN/P CMREF AVCC1
5
ML6697
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Supply Voltage Range .................. GND -0.3V to 6V Input Voltage Range Digital Inputs ...................... GND -0.3V to VCC +0.3V TPINP, TPINN, .................... GND -0.3V to VCC +0.3V Output Current TPOUTP, TPOUTN ............................................. 60mA All other outputs ................................................. 10mA Junction Temperature ............................................. 150C Storage Temperature ..............................-65C to +150C Lead Temperature (Soldering, 10 sec) .................... 260C Thermal Resistance (qJA) PLCC ............................................................... 40C/W TQFP ............................................................... 52C/W
OPERATING CONDITIONS
VCC Supply Voltage ........................................... 5V 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. TA, Ambient temperature .............................. 0C to 70C RGMSET .................................................... 9.53kW 1% RTSET ........................................................ 2.49kW 1% Receive transformer insertion loss ...................... <-0.5dB
DC ELECTRICAL CHARACTERISTICS
Over full range of operating conditions unless otherwise specified (Note 1).
SYMBOL RECEIVER VICM VID RIDR IICM IRGM IRT TPINP/N Input Common-Mode Voltage (CMREF) TPINP-TPINN Differential Input Voltage Range TPINP-TPINN Differential Input Resistance TPINP/N Common-Mode Input Current RGMSET Input Current RTSET Input Current RGMSET = 9.53kW RTSET = 2.49kW 130 500 -3.0 10.0k +10 VCC - 1.26 3.0 V V W A A A PARAMETER CONDITIONS MIN TYP MAX UNITS
LED OUTPUT (LINK100) IOLS IOHS Output Low Current Output Off Current 5 10 mA A
TRANSMITTER ITD ITOFF ITXI XERR XCMP TPOUTP/N Differential Output Current TPOUTP/N Off-State Output TPOUTP/N Differential Output Current Imbalance TPOUTP/N Differential Output Current Error TPOUTP/N Current Compliance Error Note 2, 3 RL = 200, 1% RL = 200, 1% VOUT = VCC; Note 3 VOUT = VCC 2.2V; referred to IOUT at VCC -5.0 19 0 21 1.5 500 +5.0 mA mA A %
-2.0
+2.0
%
6
ML6697
DC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS POWER SUPPLY CURRENT ICC Supply Current, Transmitting Current into all VCC pins 200 300 mA
TTL INPUTS (TXD<3:0>, TXCLKIN, MDC, MDIO, TXEN, TXER, RXEN) VIL VIH IIL IIH Input Low Voltage Input High Voltage Input Low Current Input High Current IIL = -400A IIH = 100A VIN = 0.4V VIN = 2.7V 2.0 -200 100 0.8 V V A A
MII TTL OUTPUTS (RXD<3:0>, RXCLK, RXDV, RXER, CRS, MDIO, TXCLK) VOLT VOHT Output Low Voltage Output High Voltage IOL = 4mA IOH = -4mA 2.4 0.4 V V
CMOS INPUTS (PHYAD<4:0>) VILC VIHC Input Low Voltage Input High Voltage 0.8 x VCC 0.2 x VCC V V
Note 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
7
ML6697
AC ELECTRICAL CHARACTERISTICS
Over full range of operating conditions unless otherwise specified (Note 1).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TRANSMITTER (Note 3) tTR/F tTM tTDC tTJT XOST tCLK tTXP RECEIVER tRXDC tRXDR Receive Bit Delay (CRS) Receive Bit Delay (RXDV) Note 9 Note 10 15.5 25.5 bit times bit times TPOUTP-TPOUTN Differential Rise/Fall Time TPOUTP-TPOUTN Differential Rise/Fall Time Mismatch TPOUTP-TPOUTN Differential Output Duty Cycle Distortion TPOUTP-TPOUTN Differential Output Peak-to-Peak Jitter TPOUTP-TPOUTN Differential Output Voltage Overshoot TXCLKIN - TXCLK Delay Transmit Bit Delay Note 8 Notes 5, 6; for any legal code sequence Notes 5, 6; for any legal code sequence Notes 4, 6 Note 6 Notes 6, 7 6 8 3.0 -0.5 -0.5 300 5.0 0.5 0.5 1400 5 11 10.5 ns ns ns ps % ns bit times
MII (Media-Independent Interface) XBTOL tTPWH tTPWL tRPWH tRPWL tTPS TX Output Clock Frequency Tolerance TXCLKIN pulse width HIGH TXCLKIN pulse width LOW RXCLK pulse width HIGH RXCLK pulse width LOW Setup time, TXD<3:0> Data Valid to TXCLK Rising Edge (1.4V point) Hold Time, TXD<3:0> Data Valid After TXCLK Rising Edge (1.4V point) Time that RXD<3:0> Data are Valid Before RXCLK Rising Edge (1.4V point) Time that RXD<3:0> Data are Valid After RXCLK Rising Edge (1.4V point) RXCLK 10% - 90% Rise Time RXCLK 90%-10% Fall Time RXEN high to RXD<3:0>, RXDV, RXER, RXCLK Driving RXEN low to RXD<3:0>, RXDV, RXER, RXCLK High Impedence 2 2 25MHz frequency -100 14 14 14 14 15 18 22 +100 ppm ns ns ns ns ns
tTPH
0
ns
tRCS
10
20
ns
tRCH
10
19
ns
tRPCR tRPCF tREND tRENZ
6 6 10 10
ns ns ns ns
8
ML6697
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS MDC-MDIO (MII Management Interface) tSPWS Write Setup Time, MDIO Data Valid to MDC Rising Edge 1.4V Point Write Hold Time, MDIO Data Valid After MDC Rising Edge 1.4V Point Read Setup Time, MDIO Data Valid to MDC Rising Edge 1.4V Point Read Hold Time, MDIO Data Valid After MDC Rising Edge 1.4V Point Period of MDC Pulsewidth of MDC Positive or negative pulses 10 ns
tSPWH
10
ns
tSPRS
100
ns
tSPRH
0
ns
tCPER tCPW
Note 1. Note 2.
400 160
ns ns
Note 3. Note 4. Note 5.
Note 6. Note 7.
Note 8. Note 9. Note 10.
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Measured using the test circuit shown in fig. 1, under the following conditions: RLP = 200W, RLS = 49.9W, RTSET = 2.49kW. All resistors are 1% tolerance. Output current amplitude is IOUT = 40 1.25V/RTSET. Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence. Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal voltage. The times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the effects of the external network coupling transformer and EMI/RFI emissions filter. Differential test load is shown in fig. 1 (see note 2). Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge. From first rising edge of TXCLK after TXEN goes high, to first bit of J at the MDI. From first bit of J at the MDI, to CRS. From first bit of J at the MDI, to first rising edge of RXCLK after RXDV goes high.
VCC TPOUTP RLP 200 2:1 1
RLP 200 TPOUTN RLS 49.9
2 RLS 49.9
Figure 1.
9
ML6697
TXCLKIN tTPWH tTPWL
TXCLK
TXD<3:0> TXER TXEN tTPS tTPH
Figure 2. MII Transmit Timing
tRPCR RXCLK tRPCF
RXD<3:0> RXER RXDV tRCS tRCH
Figure 3. MII Receive Timing
MDC
MDIO
tSPWS
tSPWH
Figure 4. MII Management Interface Write Timing
tCPER
MDC tSPRS tSPRH tCPW tCPW
MDIO
Figure 5. MII Management Interface Read Timing
10
ML6697
FUNCTIONAL DESCRIPTION
TRANSMIT SECTION The transmitter includes everything necessary to accept 4-bit data nibbles clocked in at 25MHz at the MII and output scrambled, 5-bit encoded MLT-3 signals into twisted pair at 100Mbps. The on-chip transmit PLL converts a 25MHz TTL-level clock at TXCLKIN to an internal 125MHz bit clock. TXCLK from the ML6697 clocks transmit data from the MAC into the ML6697's TXD<3:0> input pins upon assertion of TXEN. Data from the TXD<3:0> inputs are 5-bit encoded, scrambled, and converted from parallel to serial form at the 125MHz clock rate. The serial transmit data is converted to MLT-3 3-level code and driven differentially out of the TPOUTP and TPOUTN pins at nominal 2V levels with the proper loads. The transmitter is designed to drive a center-tapped transformer with a 2:1 winding ratio, so a differential 400W load is used on the transformer primary to properly terminate the 100W cable and termination on the secondary. The transformer's center tap must be tied to VCC. A 2:1 transformer allows using a 20mA output current. Using a 1:1 transformer would have required twice the output current and increased the on-chip power dissipation. An external 2.49kW, 1% resistor at the RTSET pin creates the correct output levels at TPOUTP/N. Driving TXER high when TXEN is high causes the H symbol (00100) to appear in scrambled MLT-3 form at TPOUTP/N. The media access controller asserts TXER synchronously with TXCLK rising edge, and the H symbol appears at least once in place of a valid symbol in the current packet. With no data at TXD<3:0> scrambled idle appears at TPOUTP/N. RECEIVE SECTION The receiver includes all necessary functions for converting 3-level MLT-3 signals from the twisted-pair media to 4-bit data nibbles at RXD<3:0> with extracted clock at RXCLK. The adaptive equalizer compensates for cable distortion and attenuation, corrects for DC baseline wander, and converts the MLT-3 signal to 2-level NRZ. The receive PLL extracts clock from the equalized signal, providing additional jitter attenuation, and clocks the signal through the serial to parallel converter. The resulting 5-bit nibbles are descrambled, aligned and decoded, and appear at RXD<3:0>. The ML6692 asserts RXDV when it's ready to present properly decoded receive data at RXD<3:0>. The extracted clock appears at RXCLK. Resistor RGMSET sets internal time constants controlling the adaptive equalizer's transfer function. RGMSET must be set to 9.53kW (1%). The receiver will assert RXER high if it detects code errors in the receive data packet, or if the idle symbols between packets are corrupted. CRS goes high whenever there is non-idle receive activity in the network. ML6697 PHY MANAGEMENT FUNCTIONS The ML6697 has management functions controlled by the register locations given in Tables 1 and 2. There are two 16-bit MII Management registers, with several unused locations. Register 0 (Table 1) is the basic control register (read/write). Register 1 (Table 2) is the basic status register (read-only). The ML6697 powers on with all management register bits set to their default values. See IEEE 802.3u section 22.2.4 for a discussion of MII management functions and status/control register definitions.
11
ML6697
MII MANAGEMENT INTERFACE REGISTERS
TABLE 1: CONTROL REGISTER
BIT(s) 0.15 0.14 0.13 0.11 0.12, 0.10-0.0 Reset Loopback Manual Speed Select Power down Not Used NAME DESCRIPTION 1 = reset all register bits to defaults 0 = normal operation 1 = PMD loopback mode 0 = normal operation 1 = 100Mb/s 0 = 10Mb/s 1 = power down 0 = normal operation R/W R/W, SC R/W RO R/W RO DEFAULT 0 0 1 0 0
TABLE 2: STATUS REGISTER
BIT(s) 1.14 1.13 1.2 1.0 1.15, 1.12-1.3, 1.1
NOTE: KEY:
NAME 100BASE-TX full duplex 100BASE-TX half duplex Link status Extended capability Not used
DESCRIPTION 1 = full duplex 100BASE-TX capability 0 = No full duplex 100BASE-TX capability 1 = half duplex 100BASE-TX capability 0 = no half duplex 100BASE-TX capability 1 = 100BASE-TX line is up 0 = 100BASE-TX link is down 1 = extended register capabilities 0 = basic register set only
R/W RO RO RO/LL RO RO
DEFAULT 0 1 latch low after link fail until read 0 0
All unnamed or unused register locations will return a 0 value when accessed. LL = latch low until read, R/W = read/write, RO = read only, SC = self-clearing.
12
NC DVCC 4 3 + C3 FB2 NC NC NC NC NC D1 7 2 1:1 1 52 51 50 49 48 47 6 5 4 3 1 2 3 C1 CMREF 46 C7 R11 TPINP 45 TPINN 44 LINK100 43 AVCC2 42 AGND2 41 TPOUTP 40 TPOUTN 39 AGND3 38 RTSET 37 RGMSET 36 AVCC3B 35 AVCC3A 34 R1 R2 C8 L1 R8 2:1 R22 R9 R19 L2 R18 R17 R16 R15 R10 4 5 6 7 8 RXTP- TXTP+ TXTP- RXTP+ C9 C10 C6 C4 C11 C12 FB1 + C5 AVCC 1
U2
2
NC
NC
NC
NC
NC
R3
TXEN TXD0
TXD1
TXD2
TXD3
AGND1
8 TXER 9 TXCLK 10 RXD3 11 DGND1 12 RXD2 13 DVCC1 14 RXD1 15 DGND2 16 RXD0 17 RXCLK 18 CRS 19 RXEN 20 DGND3
TXCLKIN
AVCC1
RJ45 SHIELD GROUNDED
ML6697 U1
CRS
U5
R21
R20
TXD3
TXD2
RXDV
DVCC2
RXER
MDC
MDIO
DGND4
DVCC5
DGND5
PHYAD0
PHYAD1
PHYAD2
PHYAD3
RXER 21 22 26 23 24 25
PHYAD4
MII INTERFACE
Figure 6. Applications Circuit
27 28 29 30 31 32 33 14 1
TXD1
TXD0
C2
TXEN
TXCLK
TXER
D6 R14 C14
RXCLK
RXDV
RXD0 10 5 9 6 8 7 D5 D2 13 12 11 U6 2 3 4 R13 C13 R24 D3 R25
RXD1
RXD2
RXD3
MDC
MDIO

RXEN
ML6697
13
ML6697
ML6697 SCHEMATIC
Figure 6 shows a general ML6697 design. The inductors L1 and L2 are for the purpose of improving return loss. Capacitor C7 is recommended. It decouples some noise at the inputs of the ML6697, and improves the Bit Error Rate (BER) performance of the board. We recommend having a 0.1F Cap on every VCC pin as indicated by C3, 4, 9-12. Also, we recommend splitting the VCC, AVCC, AGND and DGND. It is recommended that AGND and DGND planes are large enough for low inductance. If splitting the two grounds and keeping the ground planes large enough is not possible due to board space, you could join them into one larger ground plane.
ML6697 PARTS LIST
COMPONENT U1 U2 DESCRIPTION ML6697 52-Pin PLCC surface mount Can Crystal Oscillator, 25MHz 4-pin surface mount Transformer Module R21, R22 U6 FB1, FB2 L1, L2 R1 R2 R3, R24, R25 R8, R9 HEX Inverter 74HC04 Fair-Rite SM Bead P/N 2775019447 130nH inductors rated at 50MHz 2.49kW 1% 1/8W surface mount 9.53kW 1% 1/8W surface mount 750W 5% 1/8W surface mount 200W 1% 1/8W surface mount C1,C3, C4, C8-12 C5, C6 C7 C2 C13, C14 D1-D3 D5-D6 0.1F Ceramic Chip Cap 75W 5% 1/8W surface mount COMPONENT R10, R11 R13, R14 R15-R20 U5 DESCRIPTION 50W 1% 1/8W surface mount 100kW 10% 1/8W surface mount 49.9W 5% 1/8W surface mount
10mF Tantalum Cap. 10pF Cap Board layer Cap (2V rated) 22nF Cap LED Diodes Diodes Phillips PMLL 4148
14
ML6697
PHYSICAL DIMENSIONS inches (millimeters)
Package: Q52 52-Pin PLCC
0.785 - 0.795 (19.94 - 20.19) 0.750 - 0.754 (19.05 - 19.15) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22) 14
PIN 1 ID 0.750 - 0.754 0.785 - 0.795 (19.05 - 19.15) (19.94 - 20.19) 0.600 BSC (15.24 BSC) 0.690 - 0.730 (17.53 - 18.54)
40
27 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.110 (2.54 - 2.79)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
15
ML6697
PHYSICAL DIMENSIONS inches (millimeters)
Package: H64-10 64-Pin (10 x 10 x 1mm) TQFP
0.472 BSC (12.00 BSC) 0.394 BSC (10.00 BSC) 49 0 - 8 0.003 - 0.008 (0.09 - 0.20)
1 PIN 1 ID 0.394 BSC (10.00 BSC) 0.472 BSC (12.00 BSC)
33 17 0.020 BSC (0.50 BSC) 0.007 - 0.011 (0.17 - 0.27) 0.048 MAX (1.20 MAX) 0.037 - 0.041 (0.95 - 1.05)
0.018 - 0.030 (0.45 - 0.75)
SEATING PLANE
ORDERING INFORMATION
PART NUMBER ML6697CQ ML6697CH TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE 52-Pin PLCC (Q52) 64-Pin TQFP (H64-10)
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications. is a registered trademark of Micro Linear Corporation. All other trademarks are the (c) Micro Linear 2000. property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
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DS6697-01

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